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3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 1 o f 16 3g18n - rev.p001 general description the ec83 30 is a high performance positive voltage regulator designed for use in applications requiring very low input voltage and very low dropout voltage at up to 3 amps. it operates with a vin as low as 1.6v and vpp voltage 5v with output voltage programmable as low as 0.8v. the ec83 30 features ultra low dropout, ideal for applications where vout is very close to vin. additionally, the ec83 30 has an enable pin to further reduce power dissipation while shutdown. the EC8330 provides excellent regulation over variations in line, load and temperature. the ec83 30 provides a power ok signal to indicate if the voltage level of vo reaches 92% of its rating value. the ec83 30 is available in the power sop - 8 (exposed pad) pack age. it is available with 1.2v, 1.5v, 1.8v and 2.5v internally preset outputs that are also adjustable u sing external resistors. featur e s adjustable output low to 0.8v input voltage as low as 1.6v and vpp voltage 5v 240mv dropout @ 3a over current and over temperature protection enable pin low reverse leakage (output to input ) power sop - 8(ep) packages with thermal pad 2% output voltage vo power ok signal 1.2v, 1.5v, 1.8v, 2.5v options and adjustable externally using resistors vo pull low resistance when disable applications motherboards peripheral cards network cards set top boxes notebook computers pin assignments
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 2 o f 16 3g18n - rev.p001 pin description orderi n g information pin name description 1 pgood assert high once vo reaches 92% of its rating voltage. open - drain output. 2 en enable input. (active high) 3 vin input voltage. large bulk capacitance should be placed closely to this pin. a 10f ceramic capacitor is recommended at this pin. 4 vdd input voltage for controlling circuit. 5 nc not connected. 6 vout the power output of the device. a pull low resistance exists when deactivate device by ven. 7 adj this pin, ec83 30a/b when grounded, sets the output voltage by the internal feedback resistors.if external feedback resistors are used, the output voltage will be vo = 0.8(r1+r2)/r2 volts. 8 gnd reference ground. part number package marking marking information ec8 330a xxmhr sop - 8 (exposed pad) 8330a xxlll yywwt 1.xx : output voltage(ex - 12 : 1.2v;aj : adj) 2. lll : last three number of lot no 3. yyww : date code 4. t : internal tracking code EC8330b xxmhr 8330b xxlll yywwt
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 3 o f 16 3g18n - rev.p001 package types figure 1 . package types of ec 8330 function block diagram figure2:functional block diagram of ec83 30
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 4 o f 16 3g18n - rev.p001 absol u te maximum rati n gs note1: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. re co m m e nd e d o p e ra t i n g c o n d i t i o n s parameter rating unit vcntl supply voltage (vcntl to gnd) - 0.3 ~ 6 v vin supply voltage (vin to gnd) - 0.3 ~ 6 v vout to gnd voltage - 0.3 ~ vin+0.3 v pgood to gnd voltage - 0.3 ~ 7 v en, adj to gnd voltage - 0.3 ~ vcntl+0.3 v power dissipation internally limited maximum junction temperature 150 storage temperature range - 65c tj +150 lead temperature (soldering, 10sec) 260 thermal resistance junction to ambient 50 /w thermal resistance junction to case 20 /w operating temperature range - 40 to +125 storage temperature - 65 to +150 esd rating (human body model) 2000 v symbol parameter range unit vdd vcntl supply voltage 3.0 ~ 5.5 v vin vin supply voltage 1.2 ~ 5.5 v vout vout output voltage (when vcntl - vout>1.7v) 0.8 ~ vin C vdrop v iout vout output current 0~3 a r2 adj to gnd 1k ~ 24 k ? cout vout output capacitance iout = 3a at 25% nominal vout 8~770 uf iout = 1.5a at 25% nominal vout 8~1400 iout = 0.5a at 25% nominal vout 8~1700 esrcout esr of vout output capacitor 0 ~ 200 m ? ta ambient temperature - 40 ~ 85 oc tj junction temperature - 40 ~ 125 oc
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 5 o f 16 3g18n - rev.p001 electrical characteristics note:refer to the typical application circuits. these specifications apply over v cntl =5v, v in =1.8 v , v out =1.2v, and t a = - 40 ~ 85 , unless otherwise specified. typical values are at t j =25 . symbol parameter test conditions min. typ. max. unit por threshold 2.4 2.7 3 v por hysteresis 0.15 0.2 v v th_adj adjustable pin threshold i out =1ma 0.2 0.4 v v adj reference voltage i out =1ma 0.784 0.8 0.816 v v out fixed output voltage range - 2 0 +2 % v line_in line regulation(v in ) v in =v out +0.5v to 5v i out =1ma 0.2 0.6 % v load load regulation v in =v out +1v i out =1ma to 3a 0.1 1 % v drop dropout voltage i out = 3a 210 350 mv i q quiescent current v dd =5.5v 0.6 1.2 ma i lim current limit 3.2 4.5 a short circuit current v out <0.2v 0.5 1.8 a in - rush current c out =10uf,enable start - up 0.6 a v out pull - low resistance v en =0v 150 chip enable i en en input bias current v en =0v 12 ua i shdn vdd shutdown current EC8330a 10 20 ua EC8330b 1 v enl en threshold logic - low voltage - - 0.2 v logic - high voltage 1.2 power good pgood rising threshold 90 93 % pgood hysteresis 3 10 - % pgood sink capability i pgood =10ma 0.2 0.4 v pgood delay 0.5 1.5 5 ms thermal protection t sd thermal shutdown temperature - 160 - t sd thermal shutdown hysteresis - 30 - thermal shutdown temperature fold - back v out <0.4v - 110 -
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 6 o f 16 3g18n - rev.p001 typical operating characteristics dropout voltage vs. output current drop o ut voltage vs. output current current - limit vs. junction temperature short current - limit vs. junction temperature
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 7 o f 16 3g18n - rev.p001 typical operating characteristics(cont.) drop o ut voltage vs. output current drop o ut voltage vs. output current dropout voltage vs. output current reference voltage vs. junction temperature
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 8 o f 16 3g18n - rev.p001 typical operating characteristics(cont.) vcntl power supply rejection ratio(psrr) vin power supply rejection ratio(psrr)
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 9 o f 16 3g18n - rev.p001 operati n g waveforms refer to the typical application circuit. the test condition is v in =1.5v, v cntl =5v, v out =1.2v, t a = 25 unless otherwise specified power on power off c out =10 u f, c in =10 u f, r l =0.6 / time: 5ms/div c out =10 u f, c in =10 u f, r l =0.6 / time: 10ms/div ch1: v cntl , 5v/div, dc/ch2: v in , 1v/div, dc ch1: v cntl , 5v/div, dc/ch2: v in , 1v/div, dc ch3: v out , 1v/div, dc/ch4: v pok , 5v/div, dc ch3: v out , 1v/div, dc/ch4: v pok , 5v/div, dc load transient response over current protection i out =10ma to 3a to 15ma (rise / fall time = 1 u s) c out =10 u f, c in =10 u f c out =10mf, c in =10mf, i out =1a to 5.1a ch1: v out , 50mv/div, ac/ch4: i out , 1.5a/div, dc/ time: 20 u s/div ch1: v out , 1v/div, dc/ ch4: i out , 1.5a/div, dc/ time: 0.2ms/div
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 10 o f 16 3g18n - rev.p001 operati n g waveforms (cont.) refer to the typical application circuit. the test condition is v in =1.5v, v cntl =5v, v out =1.2v, t a = 2 5 unless otherwise specified shutdown enable c out =10mf, c in =10mf, r l =0.6w/ time: 5us/div c out =10mf, c in =10mf, r l =0.6w/ time: 0.5ms/div ch1: v en , 5v/div, dc/ch2: v out , 1v/div, dc ch1: v en , 5v/div, dc/ch2: v out , 1v/div, dc ch3: v pok, 5v/div, dc/ch4: i out , 3a/div, dc ch3: v pok , 5v/div, dc/ch4: i out , 3a/div, dc
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 11 o f 16 3g18n - rev.p001 typical application circuit figure3:fixed voltage regulator application circuit of EC8330a/b figure4:adjustable voltage regulat or application circuit of EC8330 a/b
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 12 o f 16 3g18n - rev.p001 function description power - on -reset a power - on - reset (por) circuit monitors both of supply voltages on vcntl and vin pins to prevent wrong logic controls. the por function initiates a soft - start process after both of the supply voltages exceed their rising por voltage thresholds during powering on. the por function also pulls low the pok voltage regardless of the output status when one of the supply voltages falls below its falling por voltage threshold. internal soft -start an internal soft - start function controls rise rate of the output voltage to limit the current surge during start - up. the typical soft - start interval is about 0.6ms. output voltage regulation an error amplifier working with a temperature compensated 0.8v reference and an output nmos regulates output to the preset voltage. the error amplifier is designed with high bandwidth and dc gain provides very fast transient response and less load regulation. it compares the reference with the feedback voltage and amplifies the difference to drive the output nmos which provides load current from vin to vout. current-limit protection the ec83 30 monitors the current flowing through the output nmos and limits the maximum current to prevent load and ec83 30 from damages during current overload conditions. short current-limit protection the short current - limit function reduces the current - limit level down to 0.8a (typical) when the voltage on adj pin falls below 0.2v (typical) during current overload or shortcircuit conditions. the short current - limit function is disabled for successful start - up during soft - start. thermal shutdown a thermal shutdown circuit limits the junction temperature of ec83 30. when the junction temperature exceeds +170 , a thermal sensor turns off the output nmos, allowing the device to cool down. the regulator regulates the output again through initiation of a new soft - start process after the junction temperature cools by 50 , resulting in a pulsed output during continuous thermal overload conditions. the thermal shutdown is designed with a 50 hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. for normal operation, the device power dissipation should be externally limited so that junction temperatures will not exceed +125 . enable control the ec83 30a/b has a dedicated enable pin (en). ec83 30a:a logic low signal applied to this pin shuts down the output. following a shutdown, a logic high signal re - enables the output through initiation of a new soft - start cycle. when left open, this pin is pulled up by an internal current source (5 u a typical) to enable normal operation. its not necessary to use an external transistor to save cost.
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 13 o f 16 3g18n - rev.p001 function description (cont.) ec83 30b: a logic low signal applied to this pin shuts down the output. following a shutdown, a logic high signal re - enables the output through initiation of a new soft - start cycle. when left open, this pin is pulled up by an internal current source (5 u a typical) to turn off operation. power - ok and delay the ec83 30 indicates the status of the output voltage by monitoring the feedback voltage (v adj ) on adj pin. as the v adj rises and reaches the rising power - ok voltage threshold(vthpok), an internal delay function starts to work. at the end of the delay time, the ic turns off the internal nmos of the pok to indicate the output is ok. as the v adj falls and reaches the falling power - ok voltage threshold, the ic turns on the nmos of the pok ( after a debounce time of 10ms typical ).
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 14 o f 16 3g18n - rev.p001 application information power sequencing the power sequencing of vin and vcntl is not necessary to be concerned. however, do not apply a voltage to vout for a long time when the main voltage applied at vin is not present. the reason is the internal parasitic diode from vout to vin conducts and dissipates power without protections due to the forward - voltage. output capacitor the ec83 30 requires a proper output capacitor to maintain stability and improve transient response. the output capacitor selection is dependent upon esr (equivalent series resistance) and capacitance of the output capacitorover the operating temperature. u u ltra - low - esr capacitors (such as ceramic chip capacitors) and low - esr bulk capacitors (such as solid tantalum, poscap, and aluminum electrolytic capacitors) can all be used as output capacitors. during load transients, the output capacitors which is depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the ec83 30 and help the device to minimize the variations of output voltage for good transient response. for the applications with large stepping load current, the low - esr bulk capacitors are normally recommended. decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. input capacitor the ec83 30 requires proper input capacitors to supply current surge during stepping load transients to prevent the input voltage rail from dropping. because the parasitic inductor from the voltage sources or other bulk capacitors to the vin pin limit the slew rate of the surge currents, more parasitic inductance needs more input capacitance. ultra - low - esr capacitors (such as ceramic chip capacitors) and low - esr bulk capacitors (such as solid tantalum, poscap, and aluminum electrolytic capacitors can all be used as an input capacitor of vin. for most applications, the recommended input c apacitance of vin is 10 u f at least. however, if the drop of the input voltage is not cared, the input capacitance can be less than 10 u f. more capacitance reduces the variations of the supply voltage on vin pin. setting the output voltage the output voltage is programmed by the resistor divider connected to a d j pin. the preset output voltage is calculated by the following equation : where r1 is the risistor connected from vout to adj with kelvin sensing connection and r2 is the risistor connected from adj to gnd. a bypass capacitor(c1) may be connected with r1 in parallel to improve load transient response and stability. o
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 15 o f 16 3g18n - rev.p001 layout consideration(see figure a) 1. please solder the exposed pad on the system ground pad on the top - layer of pcbs. the ground pad must have wide size to conduct heat into the ambient air through the system ground plane and pcb as a heat sink. 2. please place the input capacitors for vin and vcntl pins n ear the pins as close as possible for decoupling high - frequency ripples. 3. ceramic decoupling capacitors for load must be placed near the load as close as possible for decoupling high - frequency ripples. 4. to place ec83 30 and output capacitors near the load reduces parasitic resistance and inductance for excellent load transient response. 5. the negative pins of the input and output capacitors and the gnd pin must be connected to the ground plane of the load. 6. large current paths, shown by bold lines on the figure a, must have wide tracks. 7. place the r1, r2, and c1 (option) near the ec83 30 as clos as to avoid noise coupling. 8. connect the ground of the r2 to the gnd pin by using a dedicated track. 9. connect the one pin of the r1 to the load for kelvin sensing. 10. connect one pin of the c1 (option) to the vout pin figure a. thermal consideration refer to the figure b, the sop - 8(e p ) is a cost - effective package featuring a small size like a standard sop - 8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications the exposed pad must be soldered to the top - layer ground plane. it is recommended to connect the top - layer ground pad to the internal ground plan by using vias. the copper of the ground plane on the top - layer conducts heat into the pcb and ambient air. please enlarge the area of the top - layer pad and the ground plane to reduce the case - to - ambient resistance ( ca ). figure b .
3a low dropout regulator with enable EC8330 e - c m o s c o r p . ( ww w . e c m o s . c o m . t w ) p a g e 16 o f 16 3g18n - rev.p001 package information sop - 8(exposed pad) p ack a ge out l ine dimensions

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